A Fan-Out Panel Level Packaging (FOPLP) Structure Achieving Double-Sided Die Bonding Interconnects Through Copper Through-mold Vias (TMVs)

With the advancement of semiconductor devices toward high performance, high power density, and miniaturization, modern chip packaging technologies face increasingly stringent requirements for electrical performance, thermal management, and reliability. Die bonding refers to the process of tightly integrating chips with other chips or substrates/frames through physical or chemical methods. This process aims to achieve electrical interconnections, mechanical support, and thermal management between chips, forming the foundation for constructing complex integrated circuit systems (e.g., 3D integrated circuits, micro-electromechanical systems (MEMS), etc.). As a critical process in semiconductor packaging, die bonding directly impacts chip performance and system reliability. Compared to conventional bonding methods (e.g., wire bonding, Solder paste, silver epoxy), this study adopts laser ablation and electrochemical plating as the core process technologies. Copper through-mold vias (TMVs) penetrate the epoxy molding compound (EMC) layer, enabling vertical electrical connections between the chip's double-sided redistribution layers (RDLs) and external substrates. The packaging structure presented in this study effectively addresses the limitations of conventional bonding methods, the structural symmetry reduces warpage and delamination risks caused by materialstructural mismatches. While significantly enhancing thermal, electrical performance and reliability. The 10/700us surge test results of the Thyristor Surge Suppressors (TSS) samples in this study demonstrate a 28.6% improvement over the traditional SOD123 package.