Research on the interconnection reliability of substrate-like printed circuit board for AI servers

To explore the feasibility of CPU and multi-GPU expansion interconnection for AI servers, a substrate-like printed circuit board was designed, featuring 32 layers with the thickness of 4.4mm, 7th-order HDI (High-Density Interconnect), and 8 layers of 2oz power planes. It includes four interconnection schemes: high aspect ratio Through-Holes, Direct Stacked Vias, Offset Stacked Vias, and Buried-Blind Vias. An interconnection stress test platform was built to apply periodic current to coupons, measure the resistance change rate of the interconnection link in each cycle, and monitor the failure cycle counts of the four interconnection schemes. After testing, failed samples were sectioned for observation to analyze failure modes. Experimental results show that failures in high aspect ratio Through-Holes occurred in the pad area of the internal wiring layer. For the other three interconnection schemes, failures all occurred at the bottom of blind vias. Among them, Through-Holes had the worst reliability, Offset Stacked Vias had the best reliability, and Buried-Blind Vias and Direct Stacked Vias had basically the same reliability. Therefore, for the via interconnection design of AI server substrate-like boards, high aspect ratio through-holes should be avoided as much as possible, and Direct Stacked Vias or Offset Stacked Vias should be selected according to signal requirements and routing density.