A study of hotspots of the TSV-RDL interconnect structure

Through the combination of TSV and RDL interconnect lines, TSV serves as one of the core technologies for three-dimensional (3D) integration to enable vertical stacking and signal connection between chips, meeting the increasing demands for higher bandwidth and more functionality in chips. The TSV-RDL interconnect undoubtedly provides a new approach to high-density integration, yet it also brings significant challenges. Thermal management has always been an important research topic in Integrated Circuits (IC), and compared to the traditional planar IC, the 3D stacking of chips undoubtedly exacerbates this issue. The internal metal materials of the TSV-RDL interconnect structure have good thermal conductivity to transfer some of the heat generated by the chip, but the surrounding complex material layers and orders of magnitude differences in dimensions may lead to heat accumulation, causing a local hotspot and structural damage. Therefore, this study will focus on simulating and analyzing the thermal hotspots of the TSV-RDL interconnect under thermal-electric coupling, with brief observations on the distribution of current density and equivalent stress.