Thermal Behavior in Vertically Stacked Cascode GaN HEMT Power Modules including Mutual Heating, Dissipation Disturbance, and Solder Voids

Vertically stacked cascode gallium nitride (GaN) power devices provide strong electrical advantages, including reduced parasitic inductance, compact design, and high power density, compared to conventional lateral configurations. However, stacking a silicon MOSFET directly above a GaN HEMT introduces significant thermal challenges. This study identifies three major thermal issues: mutual heating between dies, restricted heat dissipation paths, and thermal degradation caused by solder voids. Finite element analysis (FEA) simulations show that the stacked design experiences approximately 30 percent higher peak temperatures than lateral counterparts due to these effects. Simulations also reveal that solder voids, especially those beneath the silicon MOSFET, disrupt vertical heat flow and intensify hot spot formation. Experimental validation using custom-fabricated modules under repeated switching operation for thermal stabilization confirms these findings. Measurements not only corroborate peak temperature trends but also introduce temperature swing per cycle as a new reliability metric. Modules with voids exhibited elevated peak temperatures and greater thermal nonuniformity, closely matching simulation results. The maximum deviation between simulated and measured temperatures was under 1.5 percent, indicating strong agreement. These results emphasize the importance of thermal aware design, void control, and packaging optimization to ensure long term reliability in next generation vertically stacked cascode GaN power modules.