A 240-/255-GHz High-Efficiency Fundamental Differential Oscillator Based on Ring Oscillator Theory in 22-nm FDSOI

This article proposes a synthesis method for a ring oscillator, which directly utilizes the transistor large-signal voltage/current (V/I) conditions and the required phase shift of each stage to calculate the element values of the embedding passive network (EPN). Accordingly, an EPN synthesis flow is outlined to allow parameter initialization for candidate oscillator structures with different stage numbers and EPN types. After comparing candidate oscillator structures, a two-stage $\boldsymbol {\Pi } $ -type-EPN differential structure is selected for the benefits of the flexible gate and drain biasing, easy power supply and grounding, and compact footprint. To maximize the oscillator dc-to-RF efficiency, a load-efficiency-oriented optimization procedure is introduced, which takes into account both the transistor large-signal behavior and the losses within the EPN and matching network (MN). As a proof of concept, two differential fundamental oscillators are fabricated by using a 22-nm FDSOI process, with a compact core size of only 0.003 mm². The 240-GHz oscillator achieves a maximum measured dc-to-RF efficiency of 5.4% with an output power of 0.626 mW and a phase noise of −94.22 dBc/Hz at a 1-MHz offset. The 255-GHz oscillator achieves a maximum efficiency of 5.72% and a phase noise of −91.35 dBc/Hz at a 1-MHz offset. To the best of our knowledge, these two oscillators achieve the highest FoM and FoM_A among the oscillators above 200 GHz.