One-Leg Half-Bridge Diode-Clamped Four-Level PWM Inverter Based on MNRV PWM

This paper introduces a one-leg half-bridge (HB) diode-clamped four-level PWM inverter incorporating the multi-neighboring reference vector pulse-width modulation (MNRV PWM) methodology. To mitigate the DC offset inherent in the one-leg HB inverter output, two approaches are proposed: the inclusion of a DC-blocking capacitor and the splitting of the central DC-link capacitor into two, with the resulting virtual neutral point connected to one end of the load. The variation in the DC-link voltage is rigorously analyzed by integrating the product of the duty cycles of the reference vectors and phase current. The proposed inverter was evaluated through simulations to assess its steady-state performance, total harmonic distortion (THD), average switching frequency, power losses per device, and voltage balancing capability, even in the presence of DC-link capacitor mismatches. Furthermore, prototype experiments were conducted to validate its fundamental operational characteristics, including its dynamic response to rapid changes in operating conditions and its voltage balancing ability under initial voltage imbalance conditions. The results demonstrated that the proposed method achieves performance comparable to a virtual-vector PWM (VVPWM) approach adapted from conventional multileg topologies, while reducing computational time by approximately 10%.