Temperature-and Bias-Dependent Capture–Emission Time Maps in Electrolyte-Gated Graphene Field-Effect Transistors

In this work, we have experimentally studied the response of electrolyte-gated graphene field-effect transistors (EG-gFETs) under various stress and relaxation conditions at different voltage bias values and temperatures. We fit all the experimental data with an analytical model based on charge trapping at the silicon oxide substrate defects in contact with the graphene channel. In the model, the electron transitions require overcoming an energetic barrier leading to the new state and, consequently, the process is temperature-and gate-bias-dependent. The fit parameters to the experimental data are then used for the first time to construct the capture–emission time maps (CET maps) of the EG-gFET devices, or the capture/emission time distribution of the oxide defects and their contribution to the device’s drift and noise at each timescale. Studying these maps as a function of the bias and temperature allows us to gain insight into the best experimental conditions to minimize electrical noise during measurements, to propose improved protocols when using EG-gFETs in applications and to guide circuit designers on deciding the best operating conditions.