A 22-nm Residual Spiking Neural Network Chip Based on Sparsity-Adaptive In-Memory Computing and a Spike-Driven Architecture

This article presents a residual spiking neural network (SNN) chip that exhibits exceptionally low power consumption and high energy efficiency (EE) to be achieved through architecture- and circuit-level co-optimizations. First, we analyze and combine the time-step-first (TSF) dataflow and in-memory computing (IMC) techniques, which are subsequently integrated into our architectural design. The fusion of the TSF and IMC methods keeps membranes spatially stationary and caches the IMC weights across all time steps. Second, to fully leverage the sparsity and event-driven nature of SNNs, we employ a fine-grained and spike-driven clock management system to minimize the power consumed by “dark silicon.” Third, at the circuit level, we introduce a sparsity-aware and clock-free IMC macro that aligns with the characteristics of SNNs. The power and latency of the IMC macro are both adaptive to spike sparsity. Furthermore, the entire IMC macro eliminates redundant power consumption from the global clock tree. To more accurately evaluate and compare SNN chips, we normalize the power and required memory space over the total number of supported synapses, i.e., power density (PD) and network density (ND). PD and ND are comprehensive indicators that simultaneously evaluate algorithms, architectures, and circuits. Compared with state-of-the-art (SOTA) works, our SNN chip improves ND by $6\times $ (to 18.18 synapses/byte) and PD by $2.3\times $ (to 0.26 nW/synapse).