An Ultralow-Energy Voltage Level Shifter With an Output-Cycle-Based Dynamic Biasing Scheme in a 130-nm CMOS Technology

This brief presents an ultralow-energy and low-propagation-delay balanced voltage level shifter (VLS) with a wide voltage conversion range. The proposed VLS achieves low propagation delay while operating with subthreshold voltage, utilizing a newly introduced dynamic biasing scheme (DBS). This scheme improves both turn-on and turn-off speeds by reducing the threshold voltage of the input device circularly. The biasing-related power consumption is largely reduced by well-designed structure. The function of the proposed VLS design has been validated by using a standard 130-nm CMOS technology, taking into account process, voltage, and temperature (PVT) variations. With the implementation of the DBS, the delay is reduced to 6.5 ns, dynamic energy is lowered to 21.7 fJ, the minimum supply voltage is 0.18 V, and the average static power consumption is 2.8 nW for a conversion from 0.3 to 1.2 V.