A Low-Cost Input-split Inverter-based Triple-Node-Upset Recoverable Latch Design

As the integration level of integrated circuits continues to increase and the feature size of nanoscale chips continues to shrink, the possibility of triple-node-upsets (TNUs) occurring in circuits increases significantly. This paper proposes a latch, namely CLTNUSL, which offers stable resilience against TNUs in radiative environments while achieving a good balance between reliability and overhead. Unlike the conventional latches consisting of multi-input C-elements, the proposed CLTNUSL latch mainly consists of 16 interlocked dual-input inverters. Due to the small number of transistors, CLTNUSL achieves low area overhead. Due to the use of high-speed paths and clock gating techniques, CLTNUSL achieves low latency and low power consumption. Simulation results demonstrate CLTNUSL’s full recovery from TNU in all scenarios. Compared with the conventional TNU-hardened latch, CLTNUSL achieves minimal latency, power consumption, area overhead, and the delay-power-area product (DPAP). CLTNUSL reduces delay by 13.22%, power by 52.74%, area by 40.90%, and DPAP by 71.44% on average, compared with state-of-the-art latches. Process-Voltage-Temperature (PVT) and Monte Carlo simulation results show that the CLTNUSL latch is less sensitive to temperature, voltage and process variations compared with conventional TNU self-recovery latches.