Low-Power Design for a Hybrid Narrowband-Broadband SoC in Electric Power Sensing Networks

To meet the demands for large-scale deployment of electric power sensing networks, spurred by China’s “Dual Carbon” goals and the advancement of the Energy Internet, this paper investigates low-power design methodologies. The focus is on the core communication System-on-Chip (SoC), which integrates both narrowband and broadband capabilities and faces significant endurance challenges when processing a wide variety of data, including small-volume narrowband and large-volume broadband traffic. This study conducts a theoretical analysis of its power consumption characteristics across different communication modes. Drawing insights from established wireless protocol optimizations and combining them with state-of-the-art low-power SoC techniques, this paper puts forward a comprehensive design solution. The proposed solution is centered on a multi-domain power management architecture that enables time-slot scheduling. It employs chip-level Discontinuous Reception (DRX) with sleep-wake mechanisms to enhance power efficiency for narrowband communications, utilizes a dynamic regulation strategy to manage broadband tasks, and implements a coordinated power state management scheme. The research herein is intended to offer theoretical foundations for developing highly energy-efficient SoCs with extended endurance for nextgeneration electric power sensing networks.