Optimal Test Point Insertion for Enhanced Small Delay Defect Coverage

Small Delay Defects (SDDs) often escape detection in traditional VLSI testing due to their minimal impact on circuit timing. Transition Delay Fault (TDF) Automatic Test Pattern Generation (ATPG) primarily propagates fault effects through shorter paths, which may not effectively detect SDDs. To enhance defect coverage, Test Point Insertion (TPI) can be utilized to influence the propagation of fault effect through longest path. This work proposes a novel TPI methodology that improves SDD detection by inserting test points in short paths, enabling fault propagation through longer paths where timing variations are more pronounced. Additionally, proper and strategic selection of the test points will lead to less area overhead and better delay test coverage. The proposed approach is evaluated on ITC'99 and IWLS benchmark circuits, demonstrating an improvement in delay test coverage, making it a promising technique for enhancing the reliability of VLSI testing.