Implementation and Optimization of High-Bandwidth IJTAG for Enhanced Test Time Reduction in Complex SoCs

The increasing complexity of modern System-onChip (SoC) designs presents a significant challenge for efficient fault testing, demanding solutions that minimize test application time while effectively utilizing Design-for-Testability (DFT) methodologies. In contrast to conventional approaches that rely on the serial application of test vectors via the IEEE Std 1687 Internal-Joint Test Action Group (IJTAG) protocol, this paper investigates the adoption of a Streaming Scan Network (SSN)-based IJTAG packet delivery methodology. This technique, termed High-Bandwidth IJTAG (HB-IJTAG), enhances testing efficiency through parallel data delivery (100 X + bandwidth gain) and enables the concurrent testing of hierarchical. This paper presents a practical case study detailing the challenges encountered during the implementation of HB-IJTAG in an industrial design environment and the strategies developed to mitigate these issues. Furthermore, architectural enhancements to the SSN based IJTAG packet delivery are proposed to achieve additional reductions in test application time. The efficacy of this methodology is demonstrated through evaluation results obtained from the industrial design highlighting a significant reduction in test time by 80-90% on certain type of tests compared to traditional testing approaches.