An Integrated Environment for Simulation of Mixed Signal Tests Using Open-Source Tools

As mixed-signal integrated circuits become more complex, testing them takes more effort, cost and time. This makes it imperative to simulate mixed-signal tests before silicon arrival however this has never been practical except for the smallest of test-cases. This results in errors in post-silicon test procedures that present a laborious and time-intensive task. This paper shows how Verilog Procedural Interface in conjunction with Python can be leveraged to create an integrated environment that enables simulations of mixed-signal ATE test procedures presilicon. Examples of how the environment plugs into the existing design flow without any disruptions and some use cases are also presented.