Exploring Tessent Two Pin Serial Port for MBIST, LBIST and ATPG for a Low Pin Count SOC

In modern chip design, optimizing pin count is critical to meeting size, cost, and performance constraints, particularly in low-pin-count, low-power SoC (System on a Chip) designs. This paper presents an efficient solution to the challenge of enabling multiple test functionalities, such as MBIST (Memory Built-In Self-Test), LBIST (Logic Built-In Self-Test), and ATPG (Automated Test Pattern Generation), through a minimal twopin interface. We propose the use of TPSP (Two Pin Serial Port), a tool-supported interface that facilitates the generation of lowpower test patterns using commercially available EDA (Electronic Design Automation) tool, ensuring seamless integration into our 5 nm low-power SoC design. This solution optimizes pin usage, enhances power efficiency, and maintains robust test coverage. Silicon results validate the approach, showing excellent correlation between pre-silicon and post-silicon power predictions, with all test patterns passing on day one.