Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes

This work proposes a new way of lowering the area ratio (AR) between the ferroelectric and metal-oxide-semiconductor (MOS) regions of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric field-effect transistors (FeFETs): the inner gate length ( $L_{\mathrm {G}}$ ) modulation. By leveraging the structural flexibility of nanosheet field-effect transistors (NSFETs), the areas of the MOS region were successfully increased by modulating the inner $L_{\mathrm {G}}$ independently from the outer $L_{\mathrm {G}}$ , achieving low AR without increasing the footprint area of the NSFETs. To validate the proposed inner $L_{\mathrm {G}}$ modulated structure, three-dimensional (3D) technology computer-aided design (TCAD) simulations were conducted. The results show that reducing the outer $L_{\mathrm {G}}$ by 2 nm while increasing the inner $L_{\mathrm {G}}$ by 2 nm effectively reduces the AR by 18 %, enhancing the memory window (MW) by 22 %. Additionally, the inner $L_{\mathrm {G}}$ modulation method enhances system-level performance, demonstrating an effective strategy for highly reliable FeFET-based embedded weight cells in advanced technology nodes.