Optimized Fpga-Accelerated Yolov8-Based Driver Drowsiness Detection System for Real-Time Embedded Automotive Applications

Ensuring driver alertness is essential for road safety, as fatigue-related accidents significantly contribute to global traffic fatalities. Prolonged driving, lack of rest, and monotonous conditions impair reaction time and decisionmaking, increasing accident risks. Existing drowsiness detection systems rely on computationally intensive deep learning models, making them unsuitable for real-time embedded automotive applications due to high power consumption. Optimized hardware implementations are needed to balance accuracy, speed, and resource efficiency. This research presents an FPGAaccelerated YOLOv8-based driver drowsiness detection system, optimized for low power consumption, efficient resource utilization, and real-time performance. The architecture was implemented on the ZYNQ-7 ZC706 FPGA using the Vivado High-Level Synthesis (HLS) tool, where channel interleaving and channel folding were employed to optimize computational efficiency and resource allocation. The design integrates several hardware modules, including Convolution, Accumulation and Activation, Max Pooling, Upsample, and YOLO-Detect, all of which were synthesized into FPGA-compatible IP (Intellectual Property) blocks for deployment. The Experimental evaluations demonstrated optimized resource utilization, with 26% LookUp Tables (LUTs), 15% Flip-Flops (FFs), 73% Block RAMs (BRAMs), and 17% Digital Signal Processors (DSPs), while maintaining a low power consumption of 9.342 W. These improvements were achieved through the applied optimization techniques, which minimized computational bottlenecks and enhanced hardware efficiency.