Power-Efficient SoC Interconnect Design with OEFNSC and Clock Gating

This paper presents a comprehensive study on the application of clock gating techniques to the Odd-Even-Full-Normal inversion considering the total Self and Coupling switching activity (OEFNSC) encoding scheme in System on Chip (SoC) designs The impact of clock gating on dynamic power consumption in OEFNSC-based interconnect systems is analyzed. Results demonstrate significant reductions in dynamic power when clock gating is applied to OEFNSC encoding. Detailed comparisons between OEFNSC implementations with and without clock gating across various data and traffic patterns are provided. The findings show that clock-gated OEFNSC achieves up to a 30% reduction in dynamic power consumption compared to non-gated OEFNSC, with an average improvement of 22% across all test scenarios. These results offer valuable insights into optimal design choices for low-power SoC interconnects, particularly in applications where energy efficiency is paramount.