A 123fs rms jitter MDLL at 8GHz with TDC-based PD and Current Variant CP

This paper presents a multiplying delay-locked loop (MDLL) that generates multiple phase differences. By using mux including delay cells in a voltage-controlled oscillator (VCO) that can make multiple-phase differences. To reduce the phase error in MDLL, this paper proposed a phase detection method that does not use a divider by comparing the reference clock and undivided output of VCO in a bang-bang phase detector (BBPD) and compares when the reference injected by using a pulser. The proposed MDLL is manufactured using 28 nm CMOS technology and operates at 8GHz with 4.2mW power consumption. The measured 123 fs rms jitter at 8 GHz with 8 multiple phases.