High-Precision, Low-Delay Approximate Multiplier Using 4-2 Compressor and Error Recovery

This paper proposes a new approximate multiplier architecture designed to improve accuracy while reducing power consumption, area, and delay compared to a conventional approximate multiplier. The proposed design utilizes a conventional approximate 4-2 compressor with truncation techniques to enhance hardware efficiency, while a proposed error recovery module is incorporated to further improve accuracy. Experimental results show that, compared to the conventional approximate multiplier and an exact multiplier, the proposed design achieves reductions in Power, Performance, Area (PPA) by 12.39% and 47.36%, respectively. It decreases Normalized Error Distance (NED), one of error metrics, and Figure of Merit (FoM) by 12.31% and 23.17%, respectively, compared to the conventional multiplier. Notably, the proposed multiplier demonstrates the most significant improvements in both delay and accuracy compared to existing approximate multipliers.