ReRAM-Based In-Memory Computation for Matrix Multiplication and Perceptron-Based Logic

Resistive RAM (ReRAM)-based in-memory computing (IMC) is a promising alternative to traditional architectures for achieving energy-efficient and high-performance computing. This study explores the implementation of matrix multiplication in ReRAM-based IMC, a fundamental operation in machine learning and AI accelerators. Various ReRAM models are analyzed, including Stanford RRAM, JART VCM v1b and JART VCM v1b var, with the latter demonstrating superior accuracy. The study further investigates different ReRAM array configuration, such as 1T1R, 2T2R, and crossbar arrays, evaluating their effectiveness in enabling parallel computation and efficient data storage. A key challenge addressed is the sneak-path problem in cross-bar architectures, which is mitigated through optimized circuit designs. Simulation results confirm that ReRAM-based matrix multiplication can significantly enhance computational efficiency, reduce power consumption, and improve memory reliability. Additionally, a perceptron-based NAND gate implementation is demonstrated, showcasing the potential of ReRAM for logic-in-memory applications.