Approximate Parallel Prefix Adder Based on Carry Substitution Algorithm

Approximate computing is a recently proposed model that shows potentiality to enhance the energy efficiency of digital systems. It is a model that operates with some amount of error and whose application is especially promising in fields where perfect precision is not required. The following paper gives a detailed discussion of the procedure of the design and simulation of a 32 bits Approximate Parallel Prefix Adder unit based on Truncated Selective Bypass Carry Substitution Algorithm (TSB-CSA). The aim is to optimize the performance; power consumption and logic complexity are currently focused on by integrating the technique of TSB-CSA into the Brent-Kung prefix adder architecture. To complete the optimization of the trade-off between accuracy and efficiency, an Adaptive Control logic has been implemented thus allowing the possibility of using approximate addition or accurate addition depending on operand significance. The intended architecture is proved to be effective by functional and timing simulations with Verilog HDL under the platform Xilinx Vivado. The findings indicate that the adder can gain significant gain in the speed and power efficiency and when used in the application program in multimedia and neural computing, the approximation levels are acceptable. This paper presents three configurations of the proposed adder using 50-50, 80-20, and 20-80 accurate to approximate ratios. The results encourage the strength of approximate adders to be used in error-tolerating tasks in systems with limited resources.