An Efficient Implementation of Small-Precision Floating-point Matrix Multiplication for AI-Based Image Processing Applications

The Multiply and Accumulator (MAC) in Convolution Neural Network (CNN) for image applications demands an efficient matrix multiplier. This study presents an area- and power-efficient implementation of floating-point matrix multiplication using 8-bit floating-point values for AI image processing applications. Maximal error analysis is employed to evaluate the impact of reduced mantissa bits. The design is written in Verilog HDL, simulated using Modelsim simulator, and verified on Intel FPGA-Quartus 20.1 to validate the functionality. The results are compared with the best published works, and the compatibility of the design with AI-based image processing using PSNR in Python is also confirmed.