Design and Implementation of Selective Adaptive Pipeline Structure for Low Power RISC Processor Applications

With Invent of computers, mobiles, Tabs, smart gaming and other multimedia devices demand for VLSI processors in semi-conductor industry and modern life is ever increasing. Now-a-days FPGAs have turn into a very important role for implementing high volume and low cost processors, applications and because of their inherent parallelism and fast processing speed. Now a days, all the portable electronic devices need to be implemented with low power architectures because of power consumption is an important consideration along with other parameters for performance. Low power consumption reduces power dissipation, increases reliability and also battery life. In this work, a low-power FPGA implementation of a RISC processor using selective adaptive pipeline is shown framework. It uses a selectively adaptive pipeline protocol(SAPP) structure that enables combining with the nearby empty stage and avoiding a redundant stage activity. It lowers the instruction set's complexity, which lowers costs, time, space, power, and heat, among other things. reduction in power dissipation as a result of all modules being locally rather than globally driven