RTL Design of Convolution for CNN Using Baugh Wooley and Wallace Tree Multipliers

This paper presents an implementation of convolution module for Convolutional Neural Network (CNN) on FPGA. The proposed hardware architecture utilizes Baugh Wooley and Wallace tree multipliers. The Baugh-Wooley algorithm is leveraged for efficient signed multiplication, while the Wallace Tree structure ensures fast partial product reduction, combining the benefits of low power consumption and reduced latency. The pipeline architecture further enhances the design by breaking down the multiplier operation into multiple stages, enabling concurrent processing and significantly improving throughput. The proposed design has been implemented on Xilinx Zynq UltraScale+ZCU106 FPGA, achieving a frequency of 769.231 MHz.