A 5T-2MTJ STT-Assisted Spin-Orbit-Torque-Based Ternary Content Addressable Memory for Hardware Accelerators

In this work, we present a novel non-volatile spin transfer torque (STT)-assisted spin–orbit torque (SOT)-based ternary content addressable memory (TCAM) with five transistors and two magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device level to the application level. At the device level, various write characteristics such as the write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bit-cells while also accounting for the impact of interconnect parasitics at the 7 nm technology node. A search error rate (SER) of $3.9 \times 10 {^{-}11 }$ is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.