A 42.5 nW, 0.5 V Differential Difference Transconductance Amplifier and Its Application in Low-Power Universal Shadow Filter

This paper presents new low-power universal shadow filters based on an enhanced CMOS structure utilizing multiple-input differential difference current transconductance amplifiers (MI-DDTAs). The multiple inputs of the DDTA are achieved through a differential pair with multiple-input MOS transistors driven simultaneously from both the gate and bulk terminals using DTMOS technique, which increases the total transconductance of the structure. Furthermore, a self-cascode configuration combining regular and low-threshold voltage (LVT) transistors is employed to achieve high output resistance comparable to a standard cascode structure, while maintaining operation in a low-voltage environment. The DDTA operates in the subthreshold region, and simulation results with a supply voltage of 0.5 V show power consumption in the nanowatt range while offering near rail-to-rail operation. The proposed universal filter offers five standard filtering functions such as low-pass filter, high-pass filter, band-pass filter, band-stop filter, and all-pass filter when an input is applied to the input. Thanks to multiple inputs of DDTA, the proposed universal filter is resistor less and it offers both non-inverting and inverting transfer functions of five standard filtering functions. The natural frequency and the quality factor can be electronically controlled by internal parameters. The proposed universal filter can be transferred to work as universal shadow filter, which can control the natural frequency and the quantity factor using external parameters. The proposed shadow filter provides both non-inverting and inverting transfer functions of five standard filtering functions, thus providing 10 filter responses from a single circuit. The natural frequency and the quality factor of all filtering functions can be electronically controlled using external amplifiers. The proposed DDTA and active filters were designed and simulated using the Cadence Virtuoso Analog Design Environment, based on TSMC’s 65-nm 1P9M CMOS technology. The MI-DDTA occupies a chip area of $171~\mu $ m $\times 119~\mu $ m.