An 18.4 GHz Low-Jitter and Fast-Locking Fractional-N Digital PLL Using Function-Reused TDC and Path-Selection BBPDs

This work presents an 18.4 GHz fractional-N digital phase-locked loop (DPLL) featuring a novel digital phase and frequency detector (PFD), which combines the functions of the time-to-digital converter (TDC) and the path-selection bang-bang phase detectors (PS-BBPDs), achieving fast-locking time and low jitter with little hardware and power overhead. During the locking transient, the PFD functions as a TDC, ensuring a large lock-in range and accelerating the locking process. In the locked state, it functions as a PS-BBPDs to compensate quantization error (QE) with minimal thermal noise. The residual QE after the PS-BBPDs is compensated by a fine digital-to-time converter (F-DTC), which only needs to cover one LSB of the PS-BBPDs, ensuring low thermal noise and better linearity. Fabricated in a 28-nm CMOS technology, the proposed DPLL employs a 100-MHz reference (REF) clock, consumes 14.83-mW power, and occupies an active area of 0.11 mm². At a fractional channel of 18.4066 GHz, it achieves an rms jitter of 124 fs. The measured worst case fractional spurs across all fractional frequency control words (FCWs) near 18.4 GHz remain below −54.8 dBc. At a frequency hopping of ±1.6 GHz, the DPLL achieves locking within 334 REF cycles ( $3.34~\mu $ s) with an accuracy of <60 ppm.