Universal Topological Arrays: An Efficient Solution for Provably Secure Hardware

Recent advances in logic locking have produced numerous schemes, many of which have been evaluated using informal methods, leaving them vulnerable to attacks. While formal frameworks for logic locking, such as universal circuits (UC), offer security against reverse engineering, their practical implementation suffers from significant overhead costs. In this work, we introduce Universal Topological Arrays, a novel, scalable alternative to traditional UC and embedded FPGA (eFPGA) designs. Our approach leverages a programmable, regular array architecture that enables efficient topological mapping of circuits while minimizing overhead. By reducing the critical path length and eliminating unnecessary supplementary circuitry, our solution addresses key limitations of existing UC and eFPGAbased methods. While also programmable, our design achieves over $10 \times$ improvement in energy efficiency compared to UC implementations, while being $2.3 \times$ smaller than minimum-sized eFPGAs. Additionally, it scales effectively with increasing circuit sizes, representing a significant step toward practical, scalable, and provably secure hardware solutions for logic locking.