Towards Improving Performance Metrics of Minority Majority Inverter Graph (mMIG) Circuits

In post-CMOS technology era, emerging data structures for logic synthesis and technology mapping have gained importance to support efficient design automation. Majority-Inverter Graph (MIG) comprise a homogeneous structure of majority and inverter nodes and has recently emerged as a prominent logic representation structure for logic synthesis and optimization. Minority-majority-inverter graph (mMIG), which comprises of majority, minority and inverter node, shows a promise in optimizing inverter count, power, and the critical delay. In this work, we improve the existing mMIG framework by refining and introducing optimized transformation rules including associativity, distributivity, swapping reconvergence, swapping non-reconvergence, relevance, and substitution for circuits with minority nodes. With mMIG-based implementations of Addition-Rotation-XOR (ARX) boxes, namely MARX-2 and SPECKEY, along with ISCAS-85 multiplier and adder circuits, we demonstrate the reduction in number of gates, inverter count, power usage, and critical delay when compared to MIG and AND-OR-inverter graph (AOIG) synthesized circuits. Our results demonstrate circuits based on mMIG achieve upto 30 to 40% reduction in gate count, in some cases the complete elimination of inverters, 20% on-chip power savings, and around 10% delay optimization over MIG and AOIG synthesis in certain typical circuits.