MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications

Edge computing applications, such as IoT and wearable devices, demand energy-efficient and high-performance hardware accelerators to support neural networks in resourceconstrained environments. This paper presents a novel MultiplyAccumulate (MAC) unit based on Most Significant Digit First (MSDF) arithmetic, designed to address these challenges. The proposed MSDF MAC unit exploits digit-level parallelism and eliminates carry propagation delays to enhance throughput and reduce energy consumption. We integrate this unit into three different widely used applications: (I) Sparse Matrix-Vector Multiplication (SpMV), (II) Multi-Layer Perceptron (MLP), and (III) Denoising Autoencoder. All designs are synthesized using TSMC 45 nm CMOS technology, and the proposed designs achieve significant improvements, including $1.69 \times$ speedup and up to 60.4% energy reduction on SpMV, and at least 39% power savings on MLP with maintained accuracy for the MLP and the autoencoder. These results demonstrate the potential of MSDFbased accelerators for efficient neural network deployment on edge devices.