3DPlace: Timing-driven Detailed Placement for Monolithic 3D ICs

D integration technologies have demonstrated significant potential for upcoming Integrated Circuits (ICs), allowing for higher performance circuits with smaller areas, by placing the components on multiple tiers. Monolithic 3D ICs exhibit even greater potential supporting greater inter-tier interconnect density compared to TSV-based 3D ICs. Although there has been some progress in the development of EDA tools for 3D ICs, the problem of detailed placement for 3D circuits has not been sufficiently addressed. Consequently, in this paper, a novel 3D timing-driven Detailed Placement algorithm is proposed. The proposed algorithm, named 3DPlace, relocates and resizes circuit components aiming to improve the circuit Worst Negative Slack (WNS). Experimental results indicate that 3DPlace achieves on average 30 % WNS improvement with negligible impact on circuit total area.