Hardware-Optimized RNN Detection for Insertion/Deletion Channels in Wireless Communication

Insertion and deletion errors pose a significant challenge in wireless communication, especially for energyconstrained Internet of Everything (IoE) devices operating in noisy 6 G environments. While traditional error-correcting codes can handle substitution errors, they fall short against synchronization distortions. In this work, we investigate a deep learning-based detection scheme for Insertion/Deletion channels, replacing sequential compute intensive classical approaches such as the Forward-Backward (FB) algorithm with a Recurrent Neural Network (RNN). The log-probabilities predicted by the neural network are forwarded to a Low-Density Parity-Check (LDPC) decoder to recover the transmitted message. To enable easy deployment of RNN on Field Programmable Gate Arrays (FPGAs), we implement a fully streaming, hardware-optimized RNN library in C++ using Vitis High-Level Systhesis (HLS). Our FPGA-based design provides flexible integration and competitive inference performance compared to related work.