FF-GFA: Flipped Folded Architecture enabled Power- and Area-Efficient Gabor Filter Design

This paper introduces a novel block-based generic filter bank architecture for Gabor filters (GF), designed to optimize area, memory storage, and power consumption while enhancing throughput. Three distinct Gabor filter architectures are implemented and evaluated, leveraging optimized fixed-point precision widths and diagonal symmetry in the filter bank. By exploiting symmetry in the filter coefficients, the number of multipliers in the convolution block is reduced, leading to substantial power savings. Additionally, memory trimming through diagonal symmetry minimizes storage requirements. To further enhance efficiency, the conventional floating-point multiplication process is replaced with reconfigurable fixed-point multipliers featuring optimized precision, and a power-gated multiplier architecture is introduced for conditional computation. The proposed filter bank architecture is synthesized on FPGA and on silicon using a 45 nm CMOS library with Genus tools, demonstrating significant improvements in area, power, delay, and memory efficiency. By employing a folded kernel and powergated multiplier architecture, the design achieves a maximum dynamic power savings of $84.6 \%, 31.34 \%$ area improvement and the highest pixel rate of $\mathbf{2 5 6 ~ M P} / \mathrm{s}$ compared to state-of-the-art designs. The results are benchmarked against existing 2D-Gabor filter implementations, showcasing substantial advancements in area, power, delay, and throughput. The hardware design files and their characteristics are made freely available for researchers and designers.