Boundary-Power Overlapped Design for Sub-3nm Standard Cell Placement

The logic block scaling is one of key elements of VLSI design. At advanced nodes, standard cells with low cell height architecture, uni-directional metal designs, and gate all around (GAA) devices have been studied. And, various mixed row placement methods are being studied to compensate for the performance degradation caused by small active areas. However, despite wide-range studies, fundamental studies for cell design are highly needed to go beyond process limitation in advanced node. In this paper, we propose a boundary-power overlapped design to overcome scaling limitation methodologically. We build up design flow including standard cell design, cell placement, and routing. We successfully demonstrate area scaling without performance degradation for area-major block. Using 214 K and 156 K instances of block, area shrinkage up to 1.4% and run-time reduction up to 17.2% were achieved in 3 nm process.