Tournament Cache Decay: Tight Control of Leakage Power for Last-Level Caches

As transistor density increases, leakage power dissipation becomes a major challenge, especially in last-level caches (LLCs), which are among the leakiest structures on a chip. Cache decay is a widely studied technique for reducing leakage power by turning off inactive (dead) cache lines. While effective in first-level caches, traditional cache decay struggles to accurately identify dead cache lines in LLCs, limiting its efficiency. This paper introduces Tournament Cache Decay (TournCD), a low-cost, feedback-driven mechanism that leverages Dynamic Set Sampling to monitor LLC performance at runtime and dynamically adjust the decay period. The unique feature of TournCD is that it offers informed decay decisions, e.g., it can be configured in a conservative manner delivering significant leakage power savings while minimizing the performance degradation (due to misclassification of cache lines as dead). Our evaluation results using SPEC2017 reveal that TournCD reduces leakage power by turning off 48.8% of cache lines in a 4MB L3 cache with a negligible (<1.59 %) increase in miss ratio. Compared to existing static and dynamic leakage reduction techniques, TournCD consistently achieves high turn-off ratios with minimal performance overheads across different cache sizes (1 MB to 8 MB).