Efficient Majority Logic Modulo 2n-1 Adder Design

The design of arithmetic circuits in beyond CMOS nanotechnologies has been of recent interest. Majority and minority gates, together with inverters, serve as the intrinsic logic primitives in a range of emerging nanotechnologies. Within the spectrum of high-performance addition schemes, parallel-prefix adder structures occupy a particularly prominent position. The design of efficient modulo $2^{n}-1$ adders is used in many applications. Therefore, efficient majority logic implementation of modulo $2^{n}-1$ parallel-prefix adders is highly desirable. In this work, majority logic implementation of existing parallel-prefix modulo $2^{n}-1$ adder architectures are presented and compared.