Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA

This paper presents an automated RegisterTransfer Level (RTL) code generator for energy-efficient oddeven merge sorting networks, optimizing hardware complexity for FPGA-based implementations. The proposed framework leverages a C -language script to dynamically generate executable Verilog Hardware Description Language (HDL), ensuring scalable and error-free comparison-exchange unit (CU) module instantiation. The architecture enhances power efficiency by employing level-wise control signals activation while maintaining high throughput through parallel sorting operations. Experimental evaluations validate the effectiveness of the design in terms of resource utilization, power efficiency, and sorting performance, making it ideal for real-time applications. Additionally, the proposed approach supports diverse sorting tasks, including maxmin and median sorting, by structuring fixed interconnections in a fully automated manner. Future work will focus on integrating pipelining techniques for further improvement.