Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware Accelerators

The Elliptic Curve Digital Signature Algorithm (ECDSA) stands as an advanced alternative to the traditional Digital Signature Algorithm (DSA), leveraging the mathematical strength of elliptic curves to deliver enhanced security and computational efficiency-particularly beneficial to resourceconstrained systems. This work explores the design of ECDSA architecture, integrating the NSGA-II optimization framework to enhance $\mathbf{G F}\left(2^{163}\right)$ Karatsuba multipliers within both signature generation and verification units. The proposed hierarchically optimized designs were synthesized on a Kintex UltraScale FPGA and evaluated on silicon using OpenROAD automation with the Nangate 45 nm standard cell library. The optimization framework identifies optimal Karatsuba multiplier sequences integrated into ECDSA architectures and benchmarked against state-of-the-art (SOTA) designs. On both FPGA and silicon, area improvement of 67.25% and 22.49%, respectively, was realized. A Figure-of-Merit (FoM) improvement of $\mathbf{4 8. 7 2 \%}$ was established for the hierarchically optimized multiplier design factored in ECDSA architectures. Up to 83.31% area-delay-product gain was achieved on silicon, marking the most significant improvement among all evaluated designs. By integrating optimized multipliers, the advanced ECDSA architecture marks a key advancement in robust hardware security. All the hardware design files are freely available for further use by designers and researchers.