Parametric RISC-V Compliant Floating-Point Arithmetic and Conversion Circuits

In the modern computing landscape, the requirements of floating-point arithmetic in different fields have diverged. Some applications require a greater level of precision and performance, while others require power-efficiency, even with a lower precision output. This paper presents floatingpoint hardware units that can be used both in RISC-V and other processor architectures. These units offer flexibility for different applications, by introducing multiple compliance modes to IEEE-754 and parametric floating-point precision and range. The proposed architecture not only envelops RISC-V features but also supports extended exception handling and additional rounding modes, to enable compatibility with as many systems as possible. The circuits are validated for all supported parameter ranges by a complete verification flow. The arithmetic circuits of addition/subtraction, multiply and accumulate, as well as conversion circuits are synthesized and the performance results indicate the benefits and competitiveness of the proposed parametric components.