A 6T SRAM based reconfigurable in-memory XOR/XNOR and accumulation architecture

In this work, we propose a 6T SRAM-based architecture for efficient in-memory “XNOR and accumulation” (XAC) and “XOR and accumulation” operations. Our design employs a split 6T SRAM cell with dual word lines (WL and WLB), enabling distinct memory and compute modes. Reverse body biasing (RBB) is applied to access transistors to reduce leakage power and prevent read disturbance during simultaneous word line activation. Unlike previous techniques limited to XNOR operations, our architecture allows dynamic selection between XOR and XNOR via an operation selection circuit. We introduce two novel accumulation designs: (1) metal-oxide-metal capacitor (MOM-CAP)-based and (2) pseudo-NMOS-based circuits. Simulations using TSMC-65nm CMOS at 1V show MOM-CAP achieves 1.74fJ energy and 0.412ns latency per XAC operation; pseudo-NMOS achieves 2.4fJ energy and 0.794ns latency. Monte Carlo analysis confirms robustness across process, voltage, and temperature variations. Finally, we demonstrate the effectiveness of our architecture in binarized neural network applications.