Efficient Tree Architecture for the Design of Static CMOS Magnitude Comparators

Magnitude comparators are of great importance in modern high-performance systems. In this paper, we propose a new, efficient tree architecture for the full custom design of magnitude comparators in static CMOS logic. This architecture provides comparator designs with reduced propagation delay times and silicon area cost. According to extended simulation results, the propagation delay is equal or reduced by up to 13% with respect to state-of-the-art 64 -bit, tree architecture, full custom design comparators. In addition, for the same 64 -bit size, silicon area comparisons show an area reduction ranging from 8% to 21%. Overall, for the 64-bit comparator designs, the power-delay-area product is reduced from $12 \%$ to $26 \%$ when the proposed design scheme is adopted.