Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits

CMOS scaling is now entering a challenging phase due to issues with lithography and device physics. Heterogeneous 3D integration technology is a cost-effective and highperformance alternative to planar integrated circuits (ICs). In this paper, we propose an on-chip power distribution network (PDN) model for heterogeneous 3D-ICs (H3D-ICs), which explicitly takes the effects of on-chip inductance into account. With this model, we can perform both transient and AC simulations efficiently. As the inductive effect is included in our model, it can also provide a precise assessment of the noise characteristics of H3D-ICs at elevated frequencies and can better answer “whatif” type questions for design space exploration in the early PDN design stage. The model is validated through HSPICE, demonstrating a maximum error of less than $1 \%$. It also shows an average increase of $1.5 x$ in transient simulation speed and an average enhancement of 8.5 x in AC simulation speed. The paper also investigates the effects of die stacking order and through silicon via (TSV) count on power supply noise (PSN) in H3D-ICs. With the proposed model, the impacts of die stacking order and TSV density on PSN can be evaluated effectively and efficiently.