An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment

Side channel attacks are becoming a major concern in the area of security, specifically in cryptographic applications. Power-based side-channel attacks are a topic of interest in research and academia because of the informative nature of power consumption. In this work, we propose an automated framework for assessing hardware design vulnerabilities against power sidechannel attacks. Our approach focuses on power-based analysis, leveraging SystemC power-aware gate models to calculate the exact power of the design during the functional simulation phase. The proposed gate models can perform online leakage analysis during functional simulations. This removes the barrier of timeconsuming decoupled power simulation and large trace signal analysis. Simulation results show that this framework achieves up to 180X speed-up in comparison to existing works with granularity of gate-level and resolution of sub-cycle, with an error of $2.5 \%$.