A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications

In this paper, we propose an accelerator architecture positioned between Coarse-Grained Reconfigurable Architectures (CGRAs) and Field Programmable Gate Arrays (FPGAs), focusing on both flexibility and power consumption. The architecture consists of a configurable network of micro-programmed processing elements (PEs) interconnected via a Quasi-Fat Tree (QFT) topology, forming a hierarchical clustered structure. It is designed to execute key Machine Learning (ML) kernels, including multi-dimensional FFT, IFFT, and matrix multiplication for fully connected layers in MLPs. The design was implemented on an Artix-7 FPGA and synthesized in 90 nm technology. Results show minimal penalties in power and clock cycles compared to a hardwired controller, positioning the architecture effectively within the reconfigurable design space.