Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications

With the upcoming 6G standard, cellular networks will see an expanded feature set, new use cases, and massive increases in key performance indicators (KPIs) for ultra-reliable low-latency communication (uRLLC) and enhanced mobile broadband (eMBB). Achieving Tbps-scale data rates with latencies as low as $\mathbf{1 0 0} \boldsymbol{\mu}$ s may require rethinking the underlying architecture. Hence, hardware acceleration at all network layers, including the data link layer (DLL), is a promising approach for achieving both high throughput and low latency. We introduce two hardware transmission (TX) buffer designs targeting the DLL of cellular networks, further referred to as SRAM-based design and register array-based (RA-based) design. We discuss their architectures and investigate read, write, and delete latencies, as well as average packet sojourn times under varying ingress rates for designs synthesized with queue counts ranging from 1 to 512, assuming round-robin read access. Our results show mean packet sojourn times as low as $\mathbf{1 5 . 5 5 4} \mathbf{~ n s}$ for specific configurations of the RA-based design at $\mathbf{3 0 \%}$ of the respective configuration’s maximum throughput, peaking at $42.669 \mu$ s when operating at 107.54 Gbps-the maximum throughput of the RA-based design with 512 queues. These findings underscore the potential of DLLlevel hardware acceleration in meeting 6G’s demanding KPIs.