EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference Designs

This paper presents EAVREF, a variability-aware evolutionary algorithm (EA)-based tool for low-power, low-voltage CMOS voltage reference (VR) designs. To ensure robustness against manufacturing process variations, the proposed framework integrates Monte Carlo simulations into the EA fitness evaluation. It supports multiple simulators, including the open-source Ngspice and commercial tools such as Hspice and Spectre. The capabilities of EAVREF are demonstrated through design examples in 28 nm, 65 nm, 90 nm, 130 nm, and 180 nm CMOS technologies, and extensive post-layout simulations were conducted to confirm the effectiveness of the approach in achieving variation-tolerant performance.