NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers

Synthesizable frequency synthesizers implemented with digital standard cells and automatic layout synthesis have demonstrated significant potential in recent studies. However, synthesizing analog mixed-signal circuits still involves manual pre- and post-layout simulation iterations, which consumes tens of hours and prolong the overall design cycle. To tackle this challenge, we propose the Non-Linear Jitter Model (NLJM), an extension of the Non-Linear Delay Model (NLDM), which incorporates phase noise information into digital standard cell models. This approach enables the application of digital design automation techniques to synthesizable analog mixed-signal timing circuits, facilitating faster design iterations. An experiment on single-stage logic gates shows that the phase noise prediction exhibits approximately 1.5dB error in the phase noise floor, and another experiment on ring oscillator planning demonstrates a maximum root mean squared (RMS) error of 1.56dB in the figure of merit (FoM). Critically, the experiments also reveal that NLJM reduces simulation time by at least 99.61% compared to the analog simulator for ring oscillator evaluations.