A 4.36 μg/√Hz 197 pJ High Linearity and Low Power Consumption Interface ASIC for MEMS Accelerometer With Physical-Stimulus-Free Built-in Self-Test (BIST)

A charge-balanced fully differential capacitive micro-electromechanical system (MEMS) accelerometer with low noise level, high energy efficiency and built-in self-test (BIST) function was developed. By applying charge-balanced architecture, the accelerometer achieves high linearity at comparatively low power. The novel C-V converter (CVC) and programmable gain amplifier (PGA) with time-multiplexed fully differential structure greatly inhibit the influence of the common-mode voltage and noise interference, enhancing the linearity and noise floor of the accelerometer. By employing time-division multiplexing, the interface application-specific integrated circuit (ASIC) proposed in this work is capable of detecting defects in both the sensing element and the interface ASIC while maintaining high precision and low noise characteristics, realizing physical-stimulus-free BIST for capacitive accelerometers. The proposed readout ASIC is fabricated in a commercial $0.18\mu $ m CMOS process. The measurement result shows that the circuit has achieved a noise floor of $4.36\mu $ g/ $\surd $ H z, an FoM of 197pJ, and a DC non-linearity of 0.06% within ±1g.