RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats

Hardware Trojan (HT) poses a critical security threat to integrated circuits, which can change circuit functionality or leak sensitive data. HTs are typically activated under low-probability conditions by exploiting “rare signals” in logic circuits. In this paper, we propose RareLS, rarity-reducing logic synthesis for mitigating HT threats. Specifically, RareLS reduces the number of rare signals through rarity-oriented technology-independent optimization and technology mapping. Experimental results show that RareLS reduces rare signals by 63.4 % on average, with a small overhead of 4.0 % in area, 1.9 % in delay, and 6.2 % in power. Moreover, RareLS complicates HT insertion for attackers by reducing HT trigger logic by 92.94 %, and aids defenders in detecting HTs by shortening the test length by more than 80.83 %.